Title :
Buried layer/connecting layer high energy implantation for improved CMOS latch-up
Author :
Morris, Wesley ; Rubin, Leonard ; Wristers, Dirk
Author_Institution :
Silicon Eng., Austin, TX, USA
Abstract :
An integrated P-buried layer formed by MeV ion implantation combined with a localized P-connecting layer has been studied for latch-up isolation improvement for advanced CMOS technology. Latch-up trigger currents have been characterized with regards to buried layer dose/energy, connecting layer dose/energy, and n-well retrograde dose. Simulation results confirmed by data indicate that P+ injection trigger currents >450 μA/μm can be achieved by utilizing certain combinations of B.L./C.L., and n-well retrograde doses for n+/p+ spacings=2.0 μm. The B.L./C.L. process architecture shows great promise for providing an alternative isolation technique far latch-up improvement that is easy to implement, and for eliminating the dependence on epi silicon for latch-up control
Keywords :
CMOS integrated circuits; buried layers; ion implantation; isolation technology; CMOS technology; P+ injection trigger current; buried layer; connecting layer; high energy ion implantation; latch-up isolation; n-well retrograde dose; CMOS process; CMOS technology; Circuits; Costs; Doping; Implants; Isolation technology; Joining processes; Oxidation; Silicon;
Conference_Titel :
Ion Implantation Technology. Proceedings of the 11th International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3289-X
DOI :
10.1109/IIT.1996.586580
