Title :
A 5-GS/s 46-dBc SFDR track and hold amplifier
Author :
Hsin-Liang Chen ; Su-Chun Cheng ; Bo-Wei Chen
Author_Institution :
Adv. Analog & Mixed-Signal IC Design Dept., Inf. & Commun. Res. Lab., Hsinchu, Taiwan
Abstract :
This paper demonstrated a 5GSample/s track and hold amplifier with 65nm CMOS process. For 6bit ADC application, this work has over 42dBc of SFDR to offer a low distorted signal. The source-degenerated source-couple amplifier with peaking inductance is employed to expand the signal swing and bandwidth, while the power dissipation is maintained as low as possible. The measured power dissipation is 48.8mW at 1.2V of supply voltage.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; sample and hold circuits; ADC; CMOS process; SFDR; analog-digital converters; power 48.8 mW; signal swing; size 65 nm; source degenerated source couple amplifier; spurious free dynamic range; track and hold amplifier; voltage 1.2 V; word length 6 bit; Bandwidth; CMOS integrated circuits; Clocks; Linearity; Resistors; Solid state circuits; Switches; source-couple; source-degenerated; track and hold amplifier;
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on
Conference_Location :
New Taipei
Print_ISBN :
978-1-4673-5083-9
Electronic_ISBN :
978-1-4673-5081-5
DOI :
10.1109/ISPACS.2012.6473567
