Title :
0.3 μm BiCMOS technology for mixed analog/digital application systems
Author :
Nii, H. ; Yoshino, T. ; Inoh, K. ; Itoh, N. ; Nakajima, H. ; Sugaya, H. ; Naruse, H. ; Katsumata, Y. ; Iwai, H.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
In this paper, 0.3 μm BiCMOS technology for mixed analog/digital application is presented. This technology includes high f max and high BVceo NPN transistor, 0.3 μm CMOS, and passive elements. These elements are successfully implemented
Keywords :
BiCMOS integrated circuits; integrated circuit measurement; large scale integration; mixed analogue-digital integrated circuits; mobile communication; 0.3 micron; BiCMOS technology; LSIs; NPN transistor; mixed analog/digital application systems; mobile communications; passive elements; Annealing; BiCMOS integrated circuits; CMOS technology; Capacitance; Electrodes; Fabrication; Inductors; Ion implantation; Isolation technology; Silicon; Substrates;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-3916-9
DOI :
10.1109/BIPOL.1997.647358
