DocumentCode :
3487308
Title :
On designing a ternary reversible circuit for online testability
Author :
Rahman, Md R. ; Rice, J.E.
Author_Institution :
Dept. of Math. & Comput. Sci., Univ. of Lethbridge, Lethbridge, AB, Canada
fYear :
2011
fDate :
23-26 Aug. 2011
Firstpage :
119
Lastpage :
124
Abstract :
Reversible logic has the potential to solve the energy efficiency problems that are beginning to create roadblocks in the continued advancement of today´s computer systems. Multiple-valued versions of reversible logic can provide even further advantages, but the current literature contains very little work on testability of such designs. This paper details work on designing an online testable block for ternary reversible logic. We build on earlier work that introduced the basic design, and provide some improvements and modifications. This block implements most ternary logic operations and is capable of testing the reversible ternary network in real time (online). The block is built entirely of reversible building blocks, thus the block is itself reversible and so multiple such blocks can be combined to construct complete, testable, ternary reversible circuits.
Keywords :
design for testability; logic gates; logic testing; ternary logic; computer systems; design for testability; energy efficiency; online testability; online testable block; reversible ternary network; ternary reversible logic; Built-in self-test; Circuit faults; Integrated circuit modeling; Logic gates; Multivalued logic; Rails; online testable circuits; reversible logic; ternary logic; two-pair two-rail checker;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and Signal Processing (PacRim), 2011 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
ISSN :
1555-5798
Print_ISBN :
978-1-4577-0252-5
Electronic_ISBN :
1555-5798
Type :
conf
DOI :
10.1109/PACRIM.2011.6032878
Filename :
6032878
Link To Document :
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