DocumentCode
3487502
Title
Design of efficient reconfigurable networks
Author
Somani, Arun K.
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
1993
fDate
13-16 Apr 1993
Firstpage
413
Lastpage
418
Abstract
The author presents a methodology to design an efficient communication reconfigurable network of processor using a circuit switching environment. He assumes that the operation is synchronous and reconfigurations occur at pre-specified times. This network is based on two architectural concepts, the generalized folding cube and the enhanced hypercube architectures. The author demonstrates the effectiveness, versatility, and flexibility of his approach
Keywords
circuit switching; hypercube networks; reconfigurable architectures; circuit switching environment; enhanced hypercube architectures; generalized folding cube; methodology; reconfigurable networks; versatility; Computer architecture; Computer networks; Costs; Delay; Hypercubes; Network topology; Parallel processing; Partitioning algorithms; Routing; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1993., Proceedings of Seventh International
Conference_Location
Newport, CA
Print_ISBN
0-8186-3442-1
Type
conf
DOI
10.1109/IPPS.1993.262918
Filename
262918
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