Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE

This paper presents a design of turbo decoder VLSI arcitecture based on 3GPP-LTE standard. In order to meet the LTE peak data rate of 326.4 Mbps, parallelization of the MAP decoder and Max-log-MAP radix-4 decoding algorithm are utilized in this work. A thorough analysis of how the MAP decoder work in parallel is presented. We describe the data dependency between each MAP decoder and hazard that cames from the usage of parallelization, in which we modify the data flow and architecture of the branch/transition metric cache memory to increase the concurrency of parallelization method and eliminate the hazard. Proposed design has a maximum throughput of 347.8 Mbps.