Bipolar process integration for a 0.25 μm BiCMOS SRAM technology using shallow trench isolation

Author

Tian, H. ; Perera, A. ; Subramanian, C. ; Pham, D. ; Damiano, J. ; Scott, J. ; McNelly, T. ; Zaman, R. ; Hayden, J.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1997

fDate

28-30 Sep 1997

Firstpage

76

Lastpage

79

Abstract

This paper describes bipolar process integration issues for a 0.25 μm BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic buried layer induced surface step at the trench edge and its impact on gate poly bridging and bipolar collector to emitter leakage; (2) elimination of end of range damage from the selectively implanted collector (SIC) implant for improved bipolar current gain; and (3) optimization of the deep collector (sinker) implant for low resistance collector formation

Keywords

BiCMOS memory circuits; SRAM chips; buried layers; ion implantation; isolation technology; 0.25 micron; BiCMOS SRAM technology; Si:As; arsenic buried layer; bipolar process integration; collector to emitter leakage; current gain; deep collector; end of range damage; gate poly bridging; selectively implanted collector; shallow trench isolation; surface step; Annealing; BiCMOS integrated circuits; Bipolar transistors; Etching; Implants; Isolation technology; Leakage current; Oxidation; Random access memory; Silicon carbide; Surface resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Conference_Location

Minneapolis, MN

ISSN

1088-9299

Print_ISBN

0-7803-3916-9

Type

conf

DOI

10.1109/BIPOL.1997.647360

Filename

647360