Low power design flow with static and statistical timing analysis

Low power design is a critical issue for the consumer electronics especially for the handhold devices. This paper employs an algorithm that searches the critical path of the logical circuit. Then, by embedding with the level converter into the original logic circuit, the proposed design can supply the lower supply voltage to circuits which are not resided on the critical path. Hence, the overall power consumption can be reduced. This paper uses the static and statistical approaches to perform the timing analysis. It can search the path sensitivity which equals to the probability of a critical path in the logic circuit. Finally, the logic gate with the proposed cell can replace the standard cell through cell-based design approach. The simulated power consumption on the ISCAS 85 benchmark circuits shows that the proposed design can reduce an average of 39% power reduction with an average of 18% delay overhead. Hence, the overall power delay product still outperform the original cell design over 25%.