DocumentCode
3487646
Title
A high-performance 128-to-1 CMOS multiplexer tree
Author
Po-Hui Yang ; Jing-Min Chen ; Kai-Shun Lin
Author_Institution
Institude of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Douliou, Taiwan
fYear
2012
fDate
4-7 Nov. 2012
Firstpage
806
Lastpage
809
Abstract
A high-performance 128-input CMOS multiplexer (MUX) tree is designed in this study. In order to enhance the speed, the high-speed feature of traditional transmission-gate MUX circuits and CMOS MUX circuits are integrated to the 128-to-1 MUX tree with high transmission speed. The circuit simulation in the CMOS 0.18μm process presents 26% reduction of delay time, comparing to the 128-to-1 MUX tree composed of traditional 2-to-1 CMOS.
Keywords
CMOS integrated circuits; multiplexing equipment; circuit simulation; delay time; high transmission speed; high-performance CMOS multiplexer tree; traditional transmission-gate MUX circuits; CMOS integrated circuits; CMOS technology; Decoding; Delay; Logic gates; Multiplexing; Transistors; MUX; multiplexer; multiplexer tree;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on
Conference_Location
New Taipei
Print_ISBN
978-1-4673-5083-9
Electronic_ISBN
978-1-4673-5081-5
Type
conf
DOI
10.1109/ISPACS.2012.6473602
Filename
6473602
Link To Document