FBT: Filled Buffer Technique to reduce code size for VLIW processors

VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated code size of the compiled application code. Therefore, reducing the application code size is a design key issue for VLIW processors. In this paper we adapt a hardware-supported approach called ldquoDeflaterdquo which has been used before in data compression. It can significantly reduce the code size compared to state-of-the-art approaches for VLIW processors as we will show within this work. In fact, we enhance the ldquoDeflaterdquo algorithm by using a new technique called Filled Buffer Technique which can be applied to any Lempel-Ziv family algorithms to improve compression ratio in average by more than 13% compared to the sole ldquoDeflaterdquo algorithm. Using our Filled Buffer Technique in conjunction with ldquoV2Frdquo improves the compression ratio by 10%. We have conducted evaluations using a representative set of benchmarks (from Mediabench and Mibench) and have applied our scheme to two VLIW processors, namely TMS320C62x and TMS320C64x. We achieved allover compression ratios as low as 44% using the ldquoDeflaterdquo algorithm (61% and 56% in average for TMS320C62x and TMS320C64x, respectively).