A three-stage 60GHz CMOS LNA using dual noise-matching technique for 5dB NF

In this paper, a three-stage LNA employing a dual noise-matching topology has been proposed. The proposed LNA has two noise-matched CS amplifiers in the first and second stages instead of the conventional cascode configuration, and the LNA realizes lower noise figure than the conventional one. The simulation results of the proposed LNA show that an input matching and output matching result less than -10 dB, a gain of 15 dB and a NF less than 5 dB are achieved at 60 GHz with a power consumption of 22 mW at a voltage of 1.2 V for the proposed LNA. Comparing with the conventional configuration, an improvement of 1.4 dB of NF has been realized at the cost of only 3 mW power increasing for almost the same gain. Both of the proposed and conventional LNA are implemented in a 90 nm CMOS process.