Author :
Vilela, G. ; Correa, E. ; Kreutz, Marcio
Author_Institution :
Dept. de Inf. e Mat. Aplic., Univ. Fed. do Rio Grande do Norte, Natal, Brazil
Abstract :
In this paper we describe the design and implementation of a compilation and code analysis toolchain for embedded systems software targeting the RISCO processor, using the LLVM project. Small systems embedded in a larger device are by far the most common kind of computational system in use today, deployed in various types of equipments. Because of their nature, an embedded system presents interesting size, efficiency and energy consumption restrictions, among others, that impose unique challenges on a project. In that scenario, the RISCO processor, a RISC architecture similar to MIPS, was created as a simple, efficient, processor that could prove to be a practical alternative to the available commercial options in its price range. The toolchain we developed permit the development, simulation and analysis of software in C and C++ for the RISCO platform, with open source tools. Besides compiling and executing high level code, the environment supports emitting control flow graphs for each module, enabling further analysis. As a case study on using CFGs and generated machine code information we developed a worst case execution time analysis tool for RISCO code. We discuss the scope of the tools, the design decisions involved in the development of the compilation and analysis system, and the results obtained through testing.
Keywords :
embedded systems; power aware computing; program compilers; program diagnostics; public domain software; reduced instruction set computing; C; C++; CFG; LLVM based development environment; MIPS; RISC architecture; RISCO processor; code analysis toolchain; compilation analysis toolchain; design decisions; embedded systems software; energy consumption restrictions; machine code information; open source tools; Assembly; Embedded systems; Optimization; Reduced instruction set computing; Registers; Testing;