DocumentCode
3488586
Title
Early Verification of Embedded Systems: Testing Automation for UML Models
Author
Wehrmeister, Marco Aurelio ; Ceron, L.M. ; da Silva, Julio L.
Author_Institution
Dept. of Comput. Sci., Santa Catarina State Univ. (UDESC), Joinville, Brazil
fYear
2012
fDate
5-7 Nov. 2012
Firstpage
119
Lastpage
124
Abstract
It is widely known that errors discovered in advanced stages of a project are expensive to fix. Therefore, it is important to look for errors as soon as possible within the design cycle. This work addresses the early verification of embedded and real-time systems based on testing the behavior specified in the high-level specifications. A tool to automate the execution of test cases on UML models is presented. Its initial goal is to support the engineers in detecting errors on the system behavior before the implementation phase. The engineers specify a set of test cases, describing: runtime scenarios; behaviors to be tested along with their input; and the expected results. The tool executes automatically each test case, reporting its success/failure as well as the obtained results. The proposed approach has been evaluated by means of a case study representing a real-world embedded system application. The achieved results demonstrate that it is feasible to test the system behavior even though when the implementation is still not available.
Keywords
Unified Modeling Language; embedded systems; program testing; program verification; UML models; design cycle; early embedded systems verification; real-time systems; real-world embedded system application; test case; testing automation; Automation; Load modeling; Real-time systems; Runtime; Testing; Unified modeling language; XML;
fLanguage
English
Publisher
ieee
Conference_Titel
Computing System Engineering (SBESC), 2012 Brazilian Symposium on
Conference_Location
Natal
ISSN
2324-7886
Print_ISBN
978-1-4673-5747-0
Type
conf
DOI
10.1109/SBESC.2012.31
Filename
6473647
Link To Document