Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs

Author

Cheng, B. ; Roy, S. ; Brown, A.R. ; Millar, C. ; Asenov, A.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

47

Lastpage

50

Abstract

The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.

Keywords

MOSFET; silicon-on-insulator; DG MOSFET; LP N-MOSFET; double gate device architectures; generation transistors; intrinsic parameter fluctuations; line edge roughness induced variability; size 22 nm; size 32 nm; size 45 nm; statistical variability; thin body SOI; Calibration; Doping profiles; Fluctuations; High-K gate dielectrics; Immune system; MOSFET circuits; Resists; Scalability; Silicon; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European

Conference_Location

Edinburgh

ISSN

1930-8876

Print_ISBN

978-1-4244-2363-7

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2008.4681695

Filename

4681695