DocumentCode
3488854
Title
RAPTOR-Design: Refactorable Architecture Processor to Optimize Recurrent Design
Author
Garcia, Paulo ; Gomes, Teresa ; Salgado, Filipe ; Cabral, J. ; Monteiro, Jose ; Tavares, A.
Author_Institution
Centro Algoritmi, Univ. of Minho, Guimaraes, Portugal
fYear
2012
fDate
5-7 Nov. 2012
Firstpage
188
Lastpage
191
Abstract
The growth in embedded systems complexity has created the demand for novel tools which allow rapid systems development and facilitate the designer´s management of complexity. Especially since systems must incorporate a variety of often contradictory characteristics, achieving design metrics in short development time is an increasing challenge. This paper presents RAPTOR-Design, a framework for System-on-Chip (SoC) design which incorporates a customizable processor architecture and allows rapid software-to-hardware migration, custom hardware integration in a tightly-coupled fashion and seamless Fault Tolerance (FT) capabilities for FPGA platforms. Impact on design metrics of processor customization, FT-capabilities and custom hardware integration are presented, as well as an overview of the design process using RAPTOR-Design.
Keywords
computational complexity; field programmable gate arrays; integrated circuit design; optimisation; reconfigurable architectures; system-on-chip; FPGA platforms; FT-capabilities; RAPTOR-Design; SoC; complexity management; design metrics; embedded systems complexity; processor customization; recurrent design optimization; refactorable architecture processor; seamless fault tolerance capabilities; system-on-chip design; Computer architecture; Detectors; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Registers; Custom Computational Units; FPGA; Microprocessor;
fLanguage
English
Publisher
ieee
Conference_Titel
Computing System Engineering (SBESC), 2012 Brazilian Symposium on
Conference_Location
Natal
ISSN
2324-7886
Print_ISBN
978-1-4673-5747-0
Type
conf
DOI
10.1109/SBESC.2012.55
Filename
6473660
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