Title :
Hardware complexity of SHA-1 and SHA-256 based on area and time analysis
Author :
Jeon, Jun-Cheol ; Seo, Kang-Joong ; Kim, Kee-Won
Author_Institution :
Dept. of Inf. Security, Woosuk Univ., Jeonbuk, South Korea
Abstract :
This paper presents the analysis of a gate-level hardware complexity of SHA-1 and SHA-256. There are several kinds of SHA series´ analysis on a hardware point of view but their analyses can be relatively measured according to the given equipments and facilities. In this paper, we provide a logical approach on hardware complexity analysis in area and time angle defined by the number of transistors needed for its construction and the time needed for the signal change to propagate through gates.
Keywords :
cryptography; SHA series analysis; SHA-1 hardware complexity; SHA-256 hardware complexity; area analysis; cryptographic hash functions; gate-level hardware complexity; time analysis; Adders; Complexity theory; Hardware; Logic gates; Registers; Security; Transistors; Area and time complexity; Hardware complexity; SHA-1; SHA-256;
Conference_Titel :
Information Networking (ICOIN), 2012 International Conference on
Conference_Location :
Bali
Print_ISBN :
978-1-4673-0251-7
DOI :
10.1109/ICOIN.2012.6164439
