Scaling of Floating Gate electrode for sub-40nm flash technologies

When scaling down Floating Gate (FG) based NAND Flash to the 40 nm-technology node and beyond, the main challenge is the electrical interference between adjacent cells. This can be drastically reduced by thinning the FG below 20 nm. For the 43 nm-node, 60 nm thick FG layers are already used [1]. In this paper we present, based on ASMpsilas Silcore^reg precursor for silicon deposition, a proof-of-concept that scaling down the floating gate thickness to 15 nm has no impact on the memory operation.