• DocumentCode
    3489315
  • Title

    A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology

  • Author

    Thomas, Olivier ; Guillaumot, Bernard ; Ernst, Thomas ; Cousin, Bastien ; Rozeau, Olivier

  • Author_Institution
    CEA-LETI/MINATEC, Grenoble
  • fYear
    2008
  • fDate
    15-19 Sept. 2008
  • Firstpage
    150
  • Lastpage
    153
  • Abstract
    This paper presents an innovative 3D CMOS 6T SRAM cell design in multi-channel (MC) FET technology by well adapting the number of channels per device. A simulation model for the 45 nm MCFET has been developed based on silicon measurements. The electrical results validated by simulations, exhibit more than 25% power dissipation reduction and 17% cell stability improvement for the same area and read access time, when compared with a standard CMOS 6T SRAM cell designed in 2D.
  • Keywords
    CMOS memory circuits; SRAM chips; field effect transistors; CMOS; SRAM cell; cell stability; multichannel FET; power dissipation reduction; silicon measurements; CMOS technology; Electrostatics; Etching; FETs; Fluctuations; Random access memory; Semiconductor device modeling; Semiconductor films; Silicon on insulator technology; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European
  • Conference_Location
    Edinburgh
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4244-2363-7
  • Electronic_ISBN
    1930-8876
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2008.4681721
  • Filename
    4681721
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3489315