VLSI implementation of discrete wavelet transform

Author

Grzeszczak, A. ; Yeap, T.H. ; Panchanathan, S.

Author_Institution

Dept. of Electr. Eng., Ottawa Univ., Ont., Canada

Volume

2

fYear

1995

fDate

5-8 Sep 1995

Firstpage

819

Abstract

This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Simulation results show that real-time coefficient calculation on a 512×612 pixels monochrome video input can be achieved

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; systolic arrays; transform coding; video coding; wavelet transforms; 262144 pixel; 512 pixel; CMOS technology; DWT; VLSI implementation; cascadable architecture; discrete wavelet transform; high-pass coefficient calculation; low-pass coefficient calculation; modular architecture; monochrome video input; multiplier; real-time coefficient calculation; simulation results; systolic architecture; Computer architecture; Discrete cosine transforms; Discrete wavelet transforms; Equations; Finite impulse response filter; Image coding; Image reconstruction; Very large scale integration; Video compression; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1995. Canadian Conference on

Conference_Location

Montreal, Que.

ISSN

0840-7789

Print_ISBN

0-7803-2766-7

Type

conf

DOI

10.1109/CCECE.1995.526421

Filename

526421