TCAD analysis for channel profile engineering with carbon doped Si (Si:C) layer for post-32 nm node bulk planar nMOSFETs

Author

Kusunoki, N. ; Hokazono, A. ; Kawanaka, S. ; Mizushima, I. ; Yoshimura, H. ; Iwai, M. ; Matsuoka, F.

Author_Institution

Toshiba Corp. Semicond. Co., Yokohama

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

178

Lastpage

181

Abstract

Carbon doped Si (Si:C) layer suppresses the boron diffusion and makes the steep channel profile; therefore, it is important to clarify the advantage of channel profile engineering using Si:C layer for the bulk planar nMOSFETs of post-32 nm technology node. In this paper, we demonstrate the merits of retrograde channel device with Si:C layer at 25 nm gate length, including the application for the bulk planar nMOSFETs with metal gate/ higher-k dielectrics by TCAD analysis.

Keywords

MOSFET; carbon; elemental semiconductors; silicon; technology CAD (electronics); Si:C; TCAD analysis; bulk planar nMOSFET; carbon doped Si layer; channel profile engineering; metal gate/ higher-k dielectrics; retrograde channel device; size 25 nm; size 32 nm; Boron; Dielectric devices; Distributed decision making; Doping; Facsimile; Hydrodynamics; Large scale integration; MOSFETs; Manufacturing processes; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European

Conference_Location

Edinburgh

ISSN

1930-8876

Print_ISBN

978-1-4244-2363-7

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2008.4681728

Filename

4681728