DocumentCode :
3489485
Title :
Impact of strain on LER variability in bulk MOSFETs
Author :
Wang, Xingsheng ; Roy, Scott ; Asenov, Asen
Author_Institution :
Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow
fYear :
2008
fDate :
15-19 Sept. 2008
Firstpage :
190
Lastpage :
193
Abstract :
This paper presents the first comprehensive three-dimensional (3D) simulation results of modern strained nMOSFETs under the influence of statistical variability, induced by gate line edge roughness (LER). The focus is the impact of strain on the LER induced variability. Stress engineering is introduced and its effects are explored. New detailed results concerning strain variability induced by LER in the channel are demonstrated, and further strain enhanced variability is captured statistically. Finally, the effects of different LER magnitude on strained devices are investigated.
Keywords :
CMOS integrated circuits; MOSFET; semiconductor device models; stress-strain relations; gate line edge roughness; statistical variability; strain variability; strained n-channel MOSFET; stress engineering; three-dimensional simulation; Calibration; Capacitive sensors; Circuit simulation; Electric variables; Fluctuations; Leakage current; Lithography; MOSFETs; Solid modeling; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European
Conference_Location :
Edinburgh
ISSN :
1930-8876
Print_ISBN :
978-1-4244-2363-7
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2008.4681730
Filename :
4681730
Link To Document :
بازگشت