DocumentCode :
3489496
Title :
On the stability of fully depleted SOI MOSFETs under lithography process variations
Author :
Kampen, Christian ; Fühner, Tim ; Burenkov, Alexander ; Erdmann, Andreas ; Lorenz, Jürgen ; Ryssel, Heiner
Author_Institution :
Fraunhofer Inst. of Integrated Syst. & Device Technol., Erlangen
fYear :
2008
fDate :
15-19 Sept. 2008
Firstpage :
194
Lastpage :
197
Abstract :
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of MOSFET devices has been evaluated by process and device simulations. FD SOI MOSFETs have been compared to bulk MOSFETs.
Keywords :
CMOS integrated circuits; MOSFET; lithography; silicon-on-insulator; CMOS devices; TCAD-based simulation; device simulations; fully depleted SOI MOSFET; lithography process-induced gate length; silicon on insulator MOSFET; Circuit simulation; Computational modeling; Doping; Lithography; MOS devices; MOSFETs; Numerical simulation; Silicon on insulator technology; Stability; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European
Conference_Location :
Edinburgh
ISSN :
1930-8876
Print_ISBN :
978-1-4244-2363-7
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2008.4681731
Filename :
4681731
Link To Document :
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