SOI CMOS front-end technology: options and tradeoffs

There is general agreement that SOI CMOS has the potential of becoming a mainstream technology for future high performance and low-power logic applications. For this to be fulfilled, SOI CMOS technology should be able to support the design and manufacturing of complex future microprocessors. Then, from the design standpoint, SOI CMOS should be nearly identical to bulk CMOS, so that design tools, methodologies, and functional blocks can all be transferred with minimal perturbation. From the manufacturing standpoint, SOI CMOS should produce acceptable yields in circuits with 10 to 100 M transistors which will require process robustness latitude, scalability, and cost equivalent to or better than bulk. From the circuit design standpoint it is generally acknowledged that fully-depleted (FD) MOSFET´s will provide the easier transfer path, because of their lack of significant floating-body (FB) effects under normal operation. However, scaled FD-MOSFET´s require very thin SOI films which pose several technological challenges. On the other hand, partially-depleted (PD) MOSFET´s are easier to make; indeed, their front-end technology can be imported from bulk with minimal perturbation. However, they display prominent FB effects which can pose problems in circuit design. The choice between the FD versus PD option is then recognized as the main SOI front-end technology tradeoff