Failure mechanism observed through static latchup simulation

This is a study on the simulation of supply overvoltage static latchup performed on CMOS devices using UTI MultiTrace System. The results showed that different latchup set-up on input pins, whether tied to Vcc, ground or open, will induce different failure mechanisms on the same DUT. Three main observations were discussed in this paper: lateral source to drain punchthrough, P-well to N-well punchthrough and oxide degradation defect. This study revealed that latchup might not cause the device to fail electrically, i.e. significant enough to fail parametric or functional test. Nevertheless, emission site could be detected at latchup sensitive location and physical defect such as thin gate oxide pinhole was observed at substrate level