High speed performance of 0.35 μm CMOS gates fabricated on low dose SIMOX substrates with/without N-well underneath the buried oxide layer

Author

Yoshino, A. ; Kumagai, K. ; Hamatake, N. ; Tatsumi, T. ; Onishi, H. ; Kurosawa, S. ; Okumura, K.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1995

fDate

3-5 Oct 1995

Firstpage

14

Lastpage

15

Abstract

High speed performances of CMOS/SIMOX circuits have been demonstrated using the low dose SIMOX substrate in spite of the thin (80nm) buried oxide layer. The following two factors have been pointed out to understand the results: (i) the depletion layer which spreads underneath the buried oxide (BOX) layer, and (ii) the Vth-lowering in the PMOS transistor due to the negative back bias (VGB=-VDD) effect. However, the correlations between the high speed performance and these two factors have not been shown in detail. In this paper, we clarify the nature of the high speed performance of the fully depleted mode ultrathin CMOS/SIMOX gates fabricated on the low dose SIMOX substrate on the basis of our experimental results

Keywords

CMOS digital integrated circuits; SIMOX; buried layers; substrates; 0.35 micron; 80 nm; N-well; PMOS transistor; Si; buried oxide layer; depletion layer; fully depleted mode; high speed performance; low dose SIMOX substrates; negative back bias effect; ultrathin CMOS/SIMOX gates; Capacitance-voltage characteristics; Capacitors; Circuits; Inverters; Leakage current; MOS devices; MOSFETs; Parasitic capacitance; Propagation delay; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1995. Proceedings., 1995 IEEE International

Conference_Location

Tucson, AZ

Print_ISBN

0-7803-2547-8

Type

conf

DOI

10.1109/SOI.1995.526437

Filename

526437