Characteristics of 1/4-μm gate ultrathin-film MOSFETs/SIMOX with tungsten-deposited low-resistance source/drain

Compared with partially depleted SOI devices, fully depleted (FD) devices have great potential for low-power high-speed ULSIs because of their advantages such as increased current drivability, excellent subthreshold slope and no kink effect. However, there are two major problems to be solved with 1/4-μm level gate devices: one is high source/drain sheet resistance associated with an ultrathin SOI film in both NMOS and PMOS, and the other is low source/drain breakdown voltage induced by parasitic bipolar action in NMOS. In this paper, it will be demonstrated that both can be improved by a self-aligned tungsten (W) layer on the source/drain in ultrathin-film (50-nm) MOSFETs/SIMOX, and the hot-carrier immunity of such devices is shown. We confirmed that the W-layer formation does not cause any changes in PMOS characteristics except a reduction of source/drain sheet resistance, so we describe results in NMOSFETs