Data structure manipulation for NNIG and PTNNIG: Towards a unified power and timing analysis

Structural representation and technology mapping of a Boolean function is an important issue in the design of digital circuits. Various data structures such as binary decision diagrams (BDDs), And inverter graphs (AIGs) and Nand Nor inverter graphs (NNIGs) have been widely used for structural representation, logic synthesis and technology mapping of digital circuits. The tool ABC has been developed for the logic synthesis and manipulation of AIGs. This paper presents a tool which builds and manipulates NNIGs as a sub-package in ABC. To the best of our understanding, it is the first tool developed for the manipulation of NNIGs. Experimental results illustrate the applicability and efficiency of the tool. The paper also presents a new data structure probabilistic timed Nand-Nor-inverter graph (PTNNIG) that can be used for accurate power estimation and timing analysis of digital circuits. Such data structures are incorporated with probability and timing as parameters and will lead to a better and combined power and timing analysis.