Design of new tiny circuits for AES encryption algorithm

Author

Dalmisli, K. Volkan ; Ors, Berna

Author_Institution

Fac. of Electr. & Electron. Eng., Istanbul Tech. Univ., Istanbul, Turkey

fYear

2009

fDate

6-8 Nov. 2009

Firstpage

1

Lastpage

5

Abstract

Advanced encryption standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

Keywords

cryptography; field programmable gate arrays; network synthesis; FPGA devices; advanced encryption standard; crypto devices; encryption algorithm; security; tiny circuits; Algorithm design and analysis; Application specific integrated circuits; Cryptography; Design engineering; Field programmable gate arrays; Maintenance engineering; Niobium; Polynomials; Radiofrequency identification; Throughput; AES; ASIC; FPGA; low area; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems (SCS), 2009 3rd International Conference on

Conference_Location

Medenine

Print_ISBN

978-1-4244-4397-0

Electronic_ISBN

978-1-4244-4398-7

Type

conf

DOI

10.1109/ICSCS.2009.5414191

Filename

5414191