An on-chip dual supply charge pump system for 45nm PD SOI eDRAM

Author

Kuang, J.B. ; Mathews, A. ; Barth, J. ; Gebara, F. ; Nguyen, T. ; Schaub, J. ; Nowka, K. ; Carpenter, G. ; Plass, D. ; Nelson, E. ; Vo, I. ; Reohr, W. ; Kirihata, T.

Author_Institution

Res. Div. & Syst.-Technol. Group, IBM, Austin, TX

fYear

2008

fDate

15-19 Sept. 2008

Firstpage

66

Lastpage

69

Abstract

We present an on-chip word line (WL) dual supply system for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficient charge transfer and energy conversion, boosting unregulated rails to 1.8x supply. At vdd=1 V, regulated high (1.5 to 1.7 V) and low (-0.3 to -0.6 V) levels ensure WL overdrive and cell turn-off, respectively, with rippling <plusmn35 mV and maintenance power <780 muW/2Mb-DRAM. The system supports >2 GHz AC array access and can endure excessive DC load.

Keywords

DRAM chips; charge pump circuits; clocks; embedded systems; reference circuits; silicon-on-insulator; switched capacitor networks; voltage regulators; PD SOI eDRAM; clock circuits; embedded DRAM applications; on-chip dual supply charge pump system; on-chip word line; reference circuits; size 45 nm; switched capacitor circuits; voltage regulators; Charge pumps; Charge transfer; Clocks; Engines; Random access memory; Regulators; Switched capacitor circuits; Switching circuits; System-on-a-chip; Voltage; SOI; eDRAM; switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European

Conference_Location

Edinburgh

ISSN

1930-8833

Print_ISBN

978-1-4244-2361-3

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2008.4681793

Filename

4681793