Title :
Total dose radiation hardening and testing issues of CMOS static memories
Author :
Hensley, R. ; Srivastava, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
Abstract :
A radiation hardened circuit should be both processed and designed for hardness. It is demonstrated that the MOSIS two micron CMOS technology exhibits radiation hardened properties, making it particularly suitable for a design methodology in which circuitry is added to compensate for the radiation induced degradation of the zero input noise margin. The non-ideal behavior of the compensation circuitry is explained and application of the circuitry in a static RAM cell is explored
Keywords :
CMOS integrated circuits; SRAM chips; compensation; integrated circuit testing; radiation hardening (electronics); semiconductor device noise; 2 micron; CMOS static memories; compensation circuitry; design methodology; radiation hardened circuit; static RAM cell; testing; total dose hardening; zero input noise margin; CMOS memory circuits; CMOS technology; Circuit noise; Circuit testing; Degradation; Equations; Inverters; MOS devices; Radiation hardening; Threshold voltage;
Conference_Titel :
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-4150-9
DOI :
10.1109/MT.1993.263140
