A low power and high performance core for planar object overlaying

The object overlaying operation is one of the most important operations in the Geographical Information Systems and spatial data application. The object overlaying is costly operation due to the amount of data processed during the performing of this operation. One technique to speed up an intensive computational operation is to implement a hardware circuit. This paper presents a low power and high performance core that can be embedded in graphical processors and applications specific chips. It demonstrates the effectiveness of prototyping a core and shows how different design decisions (such cache memory size, memory address generation...) are taken. The core has been prototyped using 0.6 μm CMOS (three metal) technology, the prototype core is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype shows that it is has a maximum delay of 3.2×10^-9 s, and the power consumption is 0.376 mW. The simulation results indicate a considerably gain in the speed up of the operation and low power consumption