• DocumentCode
    3490575
  • Title

    Effective tests for memories based on faults models for low PPM defects

  • Author

    Lam, David ; Khim, Swee Yong

  • fYear
    1993
  • fDate
    9-10 Aug 1993
  • Firstpage
    96
  • Lastpage
    101
  • Abstract
    The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented
  • Keywords
    failure analysis; fault location; integrated circuit testing; integrated memory circuits; failure modes; faults models; low PPM defects; memories; test algorithms; test pattern generation; Bonding; Circuit faults; Circuit testing; Design for testability; Electric breakdown; Fuses; Laser modes; Manufacturing; Stress; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-8186-4150-9
  • Type

    conf

  • DOI
    10.1109/MT.1993.263142
  • Filename
    263142
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3490575