Title :
A low-power concurrent multiplier-accumulator using conditional evaluation
Author :
Bartlett, V.A. ; Grass, E.
Author_Institution :
Dept. of Electron. Syst., Westminster Univ., London, UK
Abstract :
A low-power, CMOS concurrent multiplier-accumulator optimized for asynchronous DSP but also suitable for synchronous DSP applications is presented. In order to reduce the average power consumption, a technique termed conditional evaluation is used whereby addition is carried out only in rows of the carry-save array whose bit-product is non-zero. A strategy allowing operation with two´s complement numbers is introduced. Simulation results are included for a transistor-level, 16+8×8-bit implementation showing an average-case energy consumption of 25 pJ with an average delay of 7.8 ns
Keywords :
CMOS logic circuits; digital arithmetic; digital signal processing chips; low-power electronics; multiplying circuits; timing; 25 pJ; 7.8 ns; CMOS IC; asynchronous DSP applications; average power consumption reduction; carry-save array; conditional evaluation; low-power concurrent multiplier-accumulator; nonzero bit-product; self-timed implementation; synchronous DSP applications; transistor-level implementation; two´s complement numbers; Adders; Control systems; Delay; Design optimization; Digital signal processing; Energy consumption; GSM; Logic arrays; Power dissipation; Telephone sets;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.813186
