Title :
A 0.042-mm2 fully integrated analog PLL with stacked capacitor-inductor in 45nm CMOS
Author :
Yu, Shih-An ; Kinget, Peter
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY
Abstract :
We present a fully integrated Phase Locked Loop in an advanced 45 nm CMOS technology. The loop filter is integrated on chip under the voltage-controlled oscillator inductor, resulting in significant area savings. The whole PLL measures only 280 mum by 150 mum. The PLL has a dual-band output for 2-2.5 GHz and 4-5 GHz. The circuit operates from a 0.85 V supply and consumes 15.3 mW for a -120 dBc/Hz phase noise at a 1 MHz offset from a 2.0 to 2.5 GHz carrier.
Keywords :
CMOS analogue integrated circuits; MMIC; UHF integrated circuits; field effect analogue integrated circuits; low-power electronics; phase locked loops; voltage-controlled oscillators; CMOS; frequency 2 GHz to 2.5 GHz; frequency 4 GHz to 5 GHz; fully integrated analog PLL; fully integrated phase locked loop; power 15.3 mW; size 150 mum; size 280 mum; size 45 nm; stacked capacitor-inductor; voltage 0.85 V; voltage-controlled oscillator inductor; CMOS technology; Dual band; Filters; Inductors; Integrated circuit measurements; Integrated circuit technology; Phase locked loops; Phase noise; Semiconductor device measurement; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-2361-3
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2008.4681800
