Low-swing/low power driver architecture

A new low-swing/low-power CMOS driver architecture for VLSI applications is proposed. The architecture based on low swing technique using the conventional CMOS static logic. Simulation results based on the proposed design show significant improvements in both power dissipation and power-delay product compared to other low swing techniques driver architectures. Using 0.5 μm CMOS technology, for 3.3 V power supply voltage, 40% lower power dissipation than the conventional CMOS bus is achieved. The influence of the swing level on the time performance is also examined