DocumentCode
3490744
Title
Exact aliasing computation and/or aliasing free design for RAM BIST
Author
Yarmolik, V.N. ; Nicolaidis, M.
Author_Institution
TIMA/INPG, Grenoble, France
fYear
1993
fDate
9-10 Aug 1993
Firstpage
20
Lastpage
25
Abstract
Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, the authors take advantage from the regularity of the RAM test algorithms and show that exact aliasing computation and/or aliasing free signature analysis can be achieved in RAM BIST
Keywords
built-in self test; fault location; integrated circuit testing; integrated memory circuits; random-access storage; RAM BIST; RAM test algorithms; aliasing computation; aliasing free design; data compaction; fault coverage reduction; signature analysis; Algorithm design and analysis; Analytical models; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computational modeling; Information analysis; Pattern analysis; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-4150-9
Type
conf
DOI
10.1109/MT.1993.263155
Filename
263155
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