DocumentCode :
349076
Title :
Implementation of a combined high-speed interpolation and decimation wave digital filter
Author :
Ohlsson, Henrik ; Johansson, Håkan ; Wanhammar, Lars
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume :
2
fYear :
1999
fDate :
5-8 Sep 1999
Firstpage :
721
Abstract :
In this paper we discuss the design and implementation of a novel class of high-speed wave digital filter structures for interpolation and decimation. Four different structures were compared with respect to chip area, power consumption and speed. The best of these structures was combined into an interpolation and decimation filter and has been implemented using redundant arithmetic and standard cells
Keywords :
cellular arrays; digital arithmetic; high-speed integrated circuits; interpolation; wave digital filters; chip area; high-speed decimation; high-speed interpolation; power consumption; redundant arithmetic; speed; standard cells; wave digital filter; Communication cables; Digital filters; Electronic mail; Energy consumption; HDTV; Interpolation; Lattices; OFDM; Transfer functions; Wideband;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
Type :
conf
DOI :
10.1109/ICECS.1999.813210
Filename :
813210
Link To Document :
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