Efficient Stream Interface Topologies for Massively-Parallel SIMD Processing

Single-instruction multiple-data (SIMD) processing provides an efficient way to cope with the growing computational complexity of multi-media applications. One of the design challenges in massively-parallel SIMD architectures is the interface between the sequential input-output streams and the internal parallel compute engine. In this paper, three interface topologies are discussed and compared in terms of area, power and cycle overhead. Models are used to derive conclusions over the relative advantages among the topologies. Hybrid topologies that combine an SRAM and a vector register are proposed which provide more than factor two area saving with little power and cycle overhead penalty