• DocumentCode
    3490848
  • Title

    5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS

  • Author

    Von Bueren, George ; Rodoni, Lucio ; Jaeckel, Heinz ; Huber, Alex ; Brun, Roland ; Holzer, Daniel ; Schmatz, Martin

  • Author_Institution
    Electron. Lab., ETH Zurich, Zurich
  • fYear
    2008
  • fDate
    15-19 Sept. 2008
  • Firstpage
    166
  • Lastpage
    169
  • Abstract
    This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate <10-12 was verified up to 38 Gb/s using a 27-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and reference clock.
  • Keywords
    CMOS integrated circuits; clock and data recovery circuits; error statistics; integrated circuit design; network topology; bit error rate; bulk CMOS; clock/data recovery; data rate selection; quarter rate CDR; serial I/O-links; size 90 nm; Bit error rate; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Digital filters; Energy consumption; Frequency; Laboratories; Tracking loops; CMOS; clock data recovery; quarter rate;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
  • Conference_Location
    Edinburgh
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4244-2361-3
  • Electronic_ISBN
    1930-8833
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2008.4681818
  • Filename
    4681818
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3490848