DocumentCode
3490877
Title
Low voltage, low power (5:2) compressor cell for fast arithmetic circuits
Author
Gu, Jiangmin ; Chang, Chip-Hong
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
2
fYear
2003
fDate
6-10 April 2003
Abstract
This paper presents a new (5:2) compressor circuit capable of operating at ultra-low voltages. Its power efficacy is derived from the novel design of composite XOR-XNOR gate at transistor level. The new circuit eliminates the weak logic and threshold voltage drop problems, which are the main factors limiting the performance of pass transistor based circuits at low supply voltages. The proposed (5:2) compressor has been designed with special consideration on output drivability to ensure that it can function reliably at low voltages when these cells are employed in the tree structured multiplier and multiply-accumulator. Simulation results show that the proposed (5:2) compressor is able to function at supply voltage as low as 0.7 V, and. outperforms other (5:2) compressors constructed with various combinations of recently reported superior low-power logic cells.
Keywords
adders; digital arithmetic; digital signal processing chips; performance evaluation; power consumption; (5:2) compressor circuit; 0.7 V; adder; composite XOR-XNOR gate; multiply-accumulator; output drivability; performance; power efficacy; tree structured multiplier; ultra-low voltages; Adders; Arithmetic; Circuit simulation; Computational modeling; Counting circuits; Logic circuits; Low voltage; Multiplexing; Power engineering and energy; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on
ISSN
1520-6149
Print_ISBN
0-7803-7663-3
Type
conf
DOI
10.1109/ICASSP.2003.1202453
Filename
1202453
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