A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication

Author

Shi, Xintian ; Imfeld, Kilian ; Tanner, Steve ; Ansorge, Michael ; Farine, Pierre-André

Author_Institution

Inst. of Microtechnology, Neuchatel Univ.

fYear

2006

fDate

Sept. 2006

Firstpage

174

Lastpage

177

Abstract

This paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator based VCO, a dynamic-logic PFD, a 2nd order passive loop filter and a digital frequency divider. The PLL exhibits simultaneously low jitter and low power consumption. It has been integrated into a 0.35 mum CMOS process, occupying 0.09 mm² of silicon area. For a 350 MHz output frequency, the circuit features a cycle-to-cycle jitter of 7.1 ps rms and 65 ps peak-to-peak. At that frequency, the PLL consumes 12 mW from a supply voltage of 3.3 V

Keywords

CMOS integrated circuits; clocks; digital phase locked loops; frequency dividers; passive filters; silicon; timing jitter; transmitters; voltage-controlled oscillators; 0.35 micron; 12 mW; 3.3 V; 350 MHz; 7.1 ps; CMOS process; LVDS transmitter; Si; VCO; clock multiplication; digital frequency divider; dynamic-logic PFD; low-jitter CMOS PLL; low-jitter charge-pump; low-power CMOS PLL; passive loop filter; phase-locked loop; ring-oscillator; Charge pumps; Clocks; Digital filters; Frequency conversion; Jitter; Passive filters; Phase frequency detector; Phase locked loops; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307559

Filename

4099732