• DocumentCode
    3490970
  • Title

    A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

  • Author

    Kim, KyungHoon ; Yoon, SangSic ; Kwean, KiChang ; Kwon, Daehan ; Yang, SunSuk ; Park, MunPhil ; Kim, YongKi ; Chung, Byongtae

  • Author_Institution
    Memory R&D, Hynix Semicond. Inc., Ichon
  • fYear
    2008
  • fDate
    15-19 Sept. 2008
  • Firstpage
    194
  • Lastpage
    197
  • Abstract
    A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbps without using differential signaling. Major barrier to achieving high data bandwidth is the clock jitter. To overcome this limitation, this project utilizes a CML clocking scheme.
  • Keywords
    CMOS memory circuits; DRAM chips; clocks; current-mode logic; CML clock distribution network; DRAM process; GDDR5 SDRAM; bit rate 5.2 Gbit/s; size 66 nm; word length 8 bit; Clocks; Delay; Frequency; Graphics; Jitter; Phase locked loops; Pins; Random access memory; SDRAM; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
  • Conference_Location
    Edinburgh
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4244-2361-3
  • Electronic_ISBN
    1930-8833
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2008.4681825
  • Filename
    4681825
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3490970