A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

This paper presents a delta-sigma current-steering digital-to-analog converter implemented in a standard 130 nm CMOS technology. The 5-bit core DAC provides 13-bit static linearity without calibration, using only 0:44 mm². The delta-sigma converter achieves 68 dB SFDR over a 100 MHz signal bandwidth at 1 GHz sampling frequency. A novel very low power thermometer decoder was used, resulting in a power consumption of 11 mW. In terms of power efficiency this converter outperforms all comparable D/A converters published in open literature. The design demonstrates the viability of multi-bit delta-sigma D/A converters as an alternative for Nyquist-rate DACs in highly integrated broadband applications. It also shows that in deep sub-micron processes the use of a delta-sigma converter extends the usable bandwidth for D/A converters.