Digital Calibration of a Continuous-Time Cascaded ΣΔ Modulator based on Variance Derivative Estimation

This paper presents a digital calibration system for a continuous-time cascaded ΣΔ modulator. The calibration algorithm matches the digital noise cancellation filter coefficients with the integrator time constants of the analog loop filters, resulting in an optimal signal-to-quantization noise ratio. The calibration method that is proposed is based on a two-point variance estimation of the idling output data stream when zero input signals are applied. This calibration is highly insensitive to the large spread of the variance, due to the pseudo random nature of a ΣΔ modulator. The main advantages of this calibration method are the very high accuracy and very fast calibration speed, while the additional hardware costs are negligible. A 0.18mum CMOS prototype test chip has been fabricated and the measured calibration time is 0.6ms for a 10MHz, 67dB dynamic range continuous-time cascaded ΣΔ modulator.