A 3 V, 10 bit, 6.4 MHz switched-current CMOS A/D converter design

Author

Jonsson, Bengt E.

Author_Institution

Generic Radio Network Products, Ericsson Radio Syst. AB, Stockholm, Sweden

Volume

1

fYear

1998

fDate

1998

Firstpage

27

Abstract

An experimental 6.4 MS/s CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to realize a 1.5-b/stage pipelined architecture. High sampling rate and large input bandwidth were the main design objectives. The complete ADC was simulated using a SPICE level simulator. Performance is verified by analyzing the FFT of 2048 simulated samples. With f_in=3.05 MHz, the simulated SFDR=62.7 dB and SNDR=57 dB. Simulations also indicate more than 6.7 effective number of bits at f_in=15.85 MHz. Thus a high input signal bandwidth is demonstrated. Power dissipation is estimated to be less than 90 mW from a 3.0 V supply. Die area is 2.7 mm² when implemented in a 0.8 μm digital CMOS process

Keywords

CMOS integrated circuits; analogue-digital conversion; feedforward; pipeline processing; switched current circuits; 0.8 micron; 10 bit; 3 V; 6.4 MHz; 90 mW; SI CMOS A/D converter design; common-mode feedforward; digital CMOS process; first-generation SI circuits; fully-differential SI circuits; high sampling rate; large input bandwidth; pipelined architecture; switched-current CMOS ADC design; Analytical models; Bandwidth; CMOS process; Circuit simulation; Performance analysis; Power dissipation; SPICE; Sampling methods; Switching circuits; Switching converters;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813258

Filename

813258