On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45 nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.