DocumentCode
3491160
Title
Development of a load balancing tool for the GRAPE rapid prototyping environment
Author
Bilsen, G. ; Engels, M. ; Lauwereins, R. ; Peperstraete, J.A.
fYear
1993
fDate
28-30 Jun 1993
Firstpage
2
Lastpage
16
Abstract
In the graphical programming environment GRAPE-II intended for rapid prototyping of DSP ASICs on a multi-processor, a load balancing tool is required to map the different jobs of the DSP application on the multi-processor. Since most of the existing load balancing algorithms perform less well when they have to handle large or complex applications, the authors develop a tool that is better suited for such problems. This tool is based on three main techniques. (1) By exploiting the hierarchy that exists in the application graph, the complexity for each of the tools can be reduced. (2) Splitting the load balancing in sub tasks leads to three smaller search spaces instead of one big space. (3) Each of the smaller search spaces on its turn is reduced by using appropriate heuristic rules. As an example of this approach the scheduling tool and the basics of the assignment tool are presented
Keywords
application specific integrated circuits; circuit layout CAD; digital signal processing chips; multiprocessing programs; resource allocation; scheduling; DSP ASICs; DSP application; GRAPE rapid prototyping environment; application graph; assignment tool; complexity; load balancing tool; multi-processor; scheduling tool; Digital signal processing; Frequency; Load management; Parallel processing; Pipelines; Processor scheduling; Programming environments; Prototypes; Routing; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 1993. Shortening the Path from Specification to Prototype. Proceedings., Fourth International Workshop on
Conference_Location
Research Triangle Park, NC
Print_ISBN
0-8186-4300-5
Type
conf
DOI
10.1109/IWRSP.1993.263199
Filename
263199
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