An 8-bit low-power ADC array for CMOS image sensors

Author

Tanner, Steve ; Heubi, Alexandre ; Ansorge, Michael ; Pellandini, Fausto

Author_Institution

Inst. of Microtechnol., Neuchatel Univ., Switzerland

Volume

1

fYear

1998

fDate

1998

Firstpage

147

Abstract

The paper presents an original analog-to-digital converter (ADC) array meeting the constraining requirements in resolution, speed, size, and low power consumption of high-performance low-cost video cameras. The converter array is based on ADC cells relying on a cyclic redundant signed digit (RSD) algorithm supporting comparators with extended tolerance. A prototype ADC array composed of 32 converters was integrated in a 1 μm CMOS process and tested. It is featuring an 8 bit resolution for an active area of 2.1 mm², and a power consumption of 4 mW at a sampling rate of 4.2 MS/s, with a voltage supply of 2.6 V. Typical DNL and INL values of -0.5/+0.2 and ±0.4 LSB, respectively, were measured for each ADC cell. Moreover, an overall SNR of 45 dB can be achieved with a digital off-chip offset compensation

Keywords

CMOS image sensors; analogue-digital conversion; arrays; low-power electronics; video cameras; 1 micron; 2.6 V; 4 mW; 45 dB; 8 bit; CMOS image sensors; analog-to-digital converter; cyclic RSD algorithm; cyclic redundant signed digit algorithm; digital offchip offset compensation; extended tolerance comparators; low power consumption; low-cost video cameras; low-power ADC array; Analog-digital conversion; CMOS image sensors; CMOS process; Cameras; Energy consumption; Prototypes; Sampling methods; Sensor arrays; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813290

Filename

813290