Single-chip Integration of SRAM and Non-volatile Memory using Bit-line Sharing

Author

Choi, David ; Eui Pil Kwon ; Lee, Hyaeryoung ; Chang, John ; Choi, Kyu ; Villasenor, John

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA

fYear

2006

fDate

19-21 Sept. 2006

Firstpage

295

Lastpage

298

Abstract

A new memory architecture integrating SRAM and Flash within the same array is presented and demonstrated in a standard 0.25mum CMOS process with a memory access time of 20ns. Differential pair Flash cells with low programming current share the same bit-lines as SRAM cells within the same array. This enables row-to-row transfer of data between Flash and SRAM cells as well as access data through I/O directly, in return improving speed and lowering power. Area is saved through the shared usage of column decoding, sense-amplifier, and write-driver circuitry

Keywords

CMOS memory circuits; SRAM chips; amplifiers; decoding; driver circuits; flash memories; 0.25 micron; 20 ns; CMOS process; Flash memory; SRAM; bit-line sharing; column decoding; memory architecture; nonvolatile memory; row-to-row data transfer; sense-amplifier; single-chip integration; write-driver circuit; CMOS process; Manufacturing; Memory architecture; Nonvolatile memory; Random access memory; Read-write memory; SONOS devices; Split gate flash memory cells; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European

Conference_Location

Montreux

ISSN

1930-8833

Print_ISBN

1-4244-0303-0

Type

conf

DOI

10.1109/ESSCIR.2006.307589

Filename

4099762