DocumentCode
3491402
Title
A 9GHz 320Ã\x9780bit Low Leakage Microcode Read Only Memory in 65nm CMOS
Author
Hsu, Steven K. ; Agarwal, Amit ; Mathew, Sanu K. ; Krishnamurthy, Ram K. ; Hansson, Martin ; Alvandpour, Atila
Author_Institution
Circuit Res. Labs., Intel Corp., Hillsboro, OR
fYear
2006
fDate
Sept. 2006
Firstpage
299
Lastpage
302
Abstract
This paper describes a 320×80bit microcode ROM for 9GHz operation in 1.2V, 65nm CMOS technology. An extended pre-fabrication technique is proposed, which allows optimal programming of local/global merge circuitry, pre-charge devices, column-select multiplexers, and wordline driver strengths. The proposed technique enables 32% leakage and 15% total array power reduction without any delay or area penalty.
Keywords
CMOS memory circuits; firmware; read-only storage; 1.2 V; 3.2 kBytes; 65 nm; 9 GHz; CMOS memory circuit; ROM; extended pre-fabrication; low leakage microcode read only memory; optimal programming; CMOS logic circuits; CMOS memory circuits; CMOS technology; Driver circuits; Logic arrays; Logic devices; Logic programming; Multiplexing; Programmable logic arrays; Read only memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European
Conference_Location
Montreaux, Switzerland
ISSN
1930-8833
Print_ISBN
1-4244-0303-0
Type
conf
DOI
10.1109/ESSCIR.2006.307590
Filename
4099763
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